Single-Board Universal Module

I'm not expert either...but read a lot...In fact I'm interested you succeed and make this work.

The sequencing requirement seems odd PITA , can you try this on a EVAL board to see if this is critical or else?

SKY says: "The CMOS decoder should have VDD applied before a logic high is
applied to one of the control lines."

...besides the sequencing requirement. Dump that part.

The PE part states:

"Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS® devices are immune to latch-up."

This paper indicates the switches are bidirectional. Though it doesn't mention the 13384 specifically it cites other members of the family and the appendix describes the same technology (pHEMT) used in the 13384.

I am using these PE switches bi-directionally, for a receiver.
I'm not using pull-ups at all. I think this is just for the demo board to not malfunction with CMOS inputs.
You can get them from DigiKey or RFMW in the US.

for $30 you get 10 ea. 5cmx5cm boards with ENIG from seeed. Shipping?
Do you need a foot print for the PE part?

The pin out is different, not much, but enough to not make the old one work. The code is also different, for 2 and 3 ports.
OshPark seems good. I ordered boards from seeed that actually worked. The RF explorer is made by seeed, plus many other well known parts, so I'm not worried about them. They also have some eagle rules that you can use if you want. I'm not a fan of tented vias so I did not.

The oshpark 4 layer stackup is a bit different than most others. If the microstrip impedance was calculated with the OSHPark layup, that's what you should stick with. OSHPark is one of the only that I'm aware of cheap PCB manufacturers that offers a controlled impedance laminate.

I did a little more digging with the current switch.. I too was concerned that it could be a latch-up problem due to the lack of pull-down resistors on the control lines and the required power-up sequence, but there aren't any measurable power-up transients on the control lines, and adding the pull-down resistors for good measure had no effect.

There is no contradiction in that statement.
Blocking caps are built in, but have low breakdown voltage, so if you plan to apply DC to a port, add a cap. Adding a resistive load is OK for this part, but harmful for the SKY part, as it would load down the internal circuit.

An 8pF (murata GRM1555C1H8R0DZ01) would have a loss of 0.04dB at 2.44GHz. The same part would have a self-resonance at 2.56GHz thus be good at killing the signal as a bypass cap.

I'm actually using an 8pF cap already. I hadn't realised you were using 100pF. It's not going to make a 20dB difference though.

Finding the correct 50 Ohm line width is easy with TX-line and other free utilities. Controlled impedance is usually an extra cost.
The effect of some difference in impedance may not be that much, as these lines are not used for tuning, and are very short.
www.awrcorp.com/products/optional-produc...sion-line-calculator

100pF or 8pF should make no difference here, 100pF would be better at the low frequencies you don't need.

Nice!

Adding a coupling cap wont hurt, but as I remember the RFX2401 does not produce DC on pin 4 (?).

Why not pour ground over the whole board? Using OshPark's stack-up you can calculate line width and isolation with TX-line with CPW-ground. (9 mil isolation layer 1 -2?). Use the "isolate" number in the polygon setting to adjust for the CPW-ground result.
Like with a 9 mil dielectric e=4.4, 10mil gaps, and 15 mil line-width. Pins on IC's can start at 9 mil and change to 15 a bit away from the pins.

Use layer 41 "tRestrict" polygons to keep ground from pouring where you don't want it.

Keep a complete unmasked area under the chip slug, control the amount of solder paste by disallowing "cream" on SMDs, and draw you own "cream" layer on pads.
(default cream is typically too much)/

Use layer 41 "tRestrict" polygons to keep ground from pouring where you don't want it.

More ground vias can't hurt.

The two big mounting holes can be vias and assigned to VSS for making large low inductance ground vias. Some vendors charge more for un-plated holes are this is an extra process step.

The USB pads should be grounded and given vias to strengthen them. I've pulled off a few of these. For occasional programming use it may be OK.

Parasitic capacitance from ground pour can be fixed with the application of "tRestrict" polygons where needed.

Via inductance can be a problem, like in series with bypass caps where it would make bypassing less effective.
Using larger drills if possible is preferable. Minimize the use of 13 mil drills to where it only possible.
I'd rather have those inductances in parallel on poured ground than isolated.

www.saturnpcb.com/pcb_toolkit.htm

The largest current draw on the board is the RFX chip at 100mA, which is not a heavy load. Bypassing the DC feed point to that chip with- and giving good ground should be a priority. I would not be too worried about LF aspects of this. Good ground should be a higher priority. RFaxis may have some eval board layouts for this.

Cutting out ground from around the PE switch serves no purpose, and is not done in their model layout. Keep the ground solid around it.

Adding line and via inductance to the output highpass filters capacitors ground leads alters the filters response, did you run an RF simulation with these added?