Support for walkera telemetry.

int CYRF_RxPacketIsGood(u8 len)
{
    unsigned rx_state = CYRF_ReadRegister(CYRF_07_RX_IRQ_STATUS);
    if (rx_state & 0x02) {              // receive complete
        if (!(rx_state & 0x01)) {       // RXC=1, RXE=0 then 2nd check is required (debouncing)
            rx_state |= CYRF_ReadRegister(CYRF_07_RX_IRQ_STATUS);
        }
        CYRF_WriteRegister(CYRF_07_RX_IRQ_STATUS, 0x80);    // need to set RXOW before data read.
        u8 length = CYRF_ReadRegister(CYRF_09_RX_COUNT);
        if (((rx_state & 0x25) == 0x20) && length == len) {
            // good data (complete with no errors)
            return 1;
        }
        // else bad data, empty buffer
        while (length) {
            CYRF_ReadRegister(CYRF_21_RX_BUFFER);
            length--;
        }
    }
    return 0;
}

CYRF_WriteRegister(CYRF_06_RX_CFG, 0x48);

void CYRF_RX_Abort()   
{   
    if (CYRF_ReadRegister(CYRF_05_RX_CTRL) & 0x80) // We're still in receive mode    
    {   
        // Disrupt any pending receive by enabling abort    
        // Force End State should not be used to abort a receive if a SOP has already happened.    
        CYRF_WriteRegister(CYRF_29_RX_ABORT, 0x20);
        
        CYRF_RxPacketIsGood(0x10);
        
        // Abort by writing the FRC_END_STATE bit in the XACT_CFG register.    
        CYRF_WriteRegister(CYRF_0F_XACT_CFG, CYRF_ReadRegister(CYRF_0F_XACT_CFG) | 0x20);   
        
        // Disable abort
        CYRF_WriteRegister(CYRF_29_RX_ABORT, 0x00);    
    }   
}

//Set the post tx/rx state
CYRF_WriteRegister(0x0F, mode == TX_EN ? 0x28 : 0x2C);
// Wait for the FRC_END_STATE bit in the XACT_CFG register to clear
while(CYRF_ReadRegister(CYRF_0F_XACT_CFG) & 0x20) {};