Yizhan I6s does not bind
- jjk836
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29 Jul 2016 12:16 #52257
by jjk836
My ini file repository bitbucket.org/jjk836/devo10
Yizhan I6s does not bind was created by jjk836
My Yizhan i6s hexacopter does not bind to the devo10. It simply happens nothing, the LEDs continue blinking. There is a remark in the procotol list "only a single hardcoded ID". Any ideas?
My ini file repository bitbucket.org/jjk836/devo10
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- jjk836
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29 Jul 2016 18:46 #52272
by jjk836
My ini file repository bitbucket.org/jjk836/devo10
Replied by jjk836 on topic Yizhan I6s does not bind
Capture of the bind sequence of the stock tx.
www.sendspace.com/file/hv2czr
Is it normal that the miso channel shows some activity, but only in between the bytes?
Diagnostic setup:
www.sendspace.com/file/hv2czr
Is it normal that the miso channel shows some activity, but only in between the bytes?
Diagnostic setup:
My ini file repository bitbucket.org/jjk836/devo10
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- jjk836
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31 Jul 2016 20:04 #52339
by jjk836
My ini file repository bitbucket.org/jjk836/devo10
Replied by jjk836 on topic Yizhan I6s does not bind
I might misinterpret it but to me it seems the channel hopping is different than the "every other channel" which is implemented in the protocol. Or I got the sourcecode wrong. Just let me know...
0 W_REGISTER(1F) 0A 6D 67 9C 46
1 W_REGISTER(1E) 00 F6 37 5D
2 W_REGISTER(19) 01
3 W_REGISTER(1A) 45 21 EF 2C 5A 50
4 W_REGISTER(1B) 0B DF 02
5 W_REGISTER(TX_ADDR) CC CC CC CC CC
6 W_REGISTER(RX_ADDR_P0) CC CC CC CC CC
7 FLUSH_TX
8 FLUSH_RX
9 W_REGISTER(STATUS) 70
10 W_REGISTER(EN_AA) 00
11 W_REGISTER(EN_RXADDR) 01
12 W_REGISTER(SETUP_AW) 03
13 W_REGISTER(RF_CH) 07
14 W_REGISTER(SETUP_RETR) 00
15 W_REGISTER(RX_PW_P0) 09
16 W_REGISTER(RF_SETUP) 3F
17 ACTIVATE(73)
18 W_REGISTER(DYNPD) 00
19 W_REGISTER(FEATURE) 00
20 W_REGISTER(CONFIG) 8E
21 W_REGISTER(STATUS) 70
22 FLUSH_TX
23 W_REGISTER(RF_CH) 00
24 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
25 W_REGISTER(RF_CH) 02
26 W_REGISTER(STATUS) 70
27 FLUSH_TX
28 W_REGISTER(RF_CH) 02
29 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
30 W_REGISTER(RF_CH) 0C
31 W_REGISTER(STATUS) 70
32 FLUSH_TX
33 W_REGISTER(RF_CH) 0C
34 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
35 W_REGISTER(RF_CH) 16
36 W_REGISTER(STATUS) 70
37 FLUSH_TX
38 W_REGISTER(RF_CH) 16
39 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
40 W_REGISTER(RF_CH) 20
41 W_REGISTER(STATUS) 70
42 FLUSH_TX
43 W_REGISTER(RF_CH) 20
44 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
45 W_REGISTER(RF_CH) 2A
46 W_REGISTER(STATUS) 70
47 FLUSH_TX
48 W_REGISTER(RF_CH) 2A
49 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
50 W_REGISTER(RF_CH) 34
51 W_REGISTER(STATUS) 70
52 FLUSH_TX
53 W_REGISTER(RF_CH) 34
54 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
55 W_REGISTER(RF_CH) 3E
56 W_REGISTER(STATUS) 70
57 FLUSH_TX
58 W_REGISTER(RF_CH) 3E
59 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
60 W_REGISTER(RF_CH) 48
61 W_REGISTER(STATUS) 70
62 FLUSH_TX
63 W_REGISTER(RF_CH) 48
64 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
65 W_REGISTER(RF_CH) 02
66 W_REGISTER(STATUS) 70
67 FLUSH_TX
68 W_REGISTER(RF_CH) 02
69 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
70 W_REGISTER(RF_CH) 0C
71 W_REGISTER(STATUS) 70
72 FLUSH_TX
73 W_REGISTER(RF_CH) 0C
74 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
75 W_REGISTER(RF_CH) 16
76 W_REGISTER(STATUS) 70
77 FLUSH_TX
78 W_REGISTER(RF_CH) 16
79 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
80 W_REGISTER(RF_CH) 20
81 W_REGISTER(STATUS) 70
82 FLUSH_TX
83 W_REGISTER(RF_CH) 20
84 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
85 W_REGISTER(RF_CH) 2A
86 W_REGISTER(STATUS) 70
87 FLUSH_TX
88 W_REGISTER(RF_CH) 2A
89 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
90 W_REGISTER(RF_CH) 34
91 W_REGISTER(STATUS) 70
92 FLUSH_TX
93 W_REGISTER(RF_CH) 34
94 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
95 W_REGISTER(RF_CH) 3E
96 W_REGISTER(STATUS) 70
97 FLUSH_TX
98 W_REGISTER(RF_CH) 3E
99 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
100 W_REGISTER(RF_CH) 48
101 W_REGISTER(STATUS) 70
102 FLUSH_TX
103 W_REGISTER(RF_CH) 48
104 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
105 W_REGISTER(RF_CH) 02
106 W_REGISTER(STATUS) 70
107 FLUSH_TX
108 W_REGISTER(RF_CH) 02
109 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
110 W_REGISTER(RF_CH) 0C
111 W_REGISTER(STATUS) 70
112 FLUSH_TX
113 W_REGISTER(RF_CH) 0C
114 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
115 W_REGISTER(RF_CH) 16
116 W_REGISTER(STATUS) 70
117 FLUSH_TX
python nRF24_decode.py i6s/s1.csv | grep RF_CH | awk '{ print rshift(strtonum("0x" $3),2) }'
1
0
0
0
3
3
5
5
8
8
10
10
13
13
15
15
18
18
0
0
3
3
5
5
8
8
10
10
13
13
15
15
18
18
0
0
3
3
5
5
8
8
10
10
13
13
15
15
18
18
0
0
3
3
5
5
8
8
10
10
13
13
15
15
18
18
0
0
3
3
5
5
8
8
10
10
13
13
15
15
18
18
0
0
3
3
5
5
8
8
10
10
13
13
15
15
18
18
0
0
3
3
0 W_REGISTER(1F) 0A 6D 67 9C 46
1 W_REGISTER(1E) 00 F6 37 5D
2 W_REGISTER(19) 01
3 W_REGISTER(1A) 45 21 EF 2C 5A 50
4 W_REGISTER(1B) 0B DF 02
5 W_REGISTER(TX_ADDR) CC CC CC CC CC
6 W_REGISTER(RX_ADDR_P0) CC CC CC CC CC
7 FLUSH_TX
8 FLUSH_RX
9 W_REGISTER(STATUS) 70
10 W_REGISTER(EN_AA) 00
11 W_REGISTER(EN_RXADDR) 01
12 W_REGISTER(SETUP_AW) 03
13 W_REGISTER(RF_CH) 07
14 W_REGISTER(SETUP_RETR) 00
15 W_REGISTER(RX_PW_P0) 09
16 W_REGISTER(RF_SETUP) 3F
17 ACTIVATE(73)
18 W_REGISTER(DYNPD) 00
19 W_REGISTER(FEATURE) 00
20 W_REGISTER(CONFIG) 8E
21 W_REGISTER(STATUS) 70
22 FLUSH_TX
23 W_REGISTER(RF_CH) 00
24 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
25 W_REGISTER(RF_CH) 02
26 W_REGISTER(STATUS) 70
27 FLUSH_TX
28 W_REGISTER(RF_CH) 02
29 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
30 W_REGISTER(RF_CH) 0C
31 W_REGISTER(STATUS) 70
32 FLUSH_TX
33 W_REGISTER(RF_CH) 0C
34 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
35 W_REGISTER(RF_CH) 16
36 W_REGISTER(STATUS) 70
37 FLUSH_TX
38 W_REGISTER(RF_CH) 16
39 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
40 W_REGISTER(RF_CH) 20
41 W_REGISTER(STATUS) 70
42 FLUSH_TX
43 W_REGISTER(RF_CH) 20
44 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
45 W_REGISTER(RF_CH) 2A
46 W_REGISTER(STATUS) 70
47 FLUSH_TX
48 W_REGISTER(RF_CH) 2A
49 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
50 W_REGISTER(RF_CH) 34
51 W_REGISTER(STATUS) 70
52 FLUSH_TX
53 W_REGISTER(RF_CH) 34
54 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
55 W_REGISTER(RF_CH) 3E
56 W_REGISTER(STATUS) 70
57 FLUSH_TX
58 W_REGISTER(RF_CH) 3E
59 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
60 W_REGISTER(RF_CH) 48
61 W_REGISTER(STATUS) 70
62 FLUSH_TX
63 W_REGISTER(RF_CH) 48
64 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
65 W_REGISTER(RF_CH) 02
66 W_REGISTER(STATUS) 70
67 FLUSH_TX
68 W_REGISTER(RF_CH) 02
69 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
70 W_REGISTER(RF_CH) 0C
71 W_REGISTER(STATUS) 70
72 FLUSH_TX
73 W_REGISTER(RF_CH) 0C
74 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
75 W_REGISTER(RF_CH) 16
76 W_REGISTER(STATUS) 70
77 FLUSH_TX
78 W_REGISTER(RF_CH) 16
79 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
80 W_REGISTER(RF_CH) 20
81 W_REGISTER(STATUS) 70
82 FLUSH_TX
83 W_REGISTER(RF_CH) 20
84 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
85 W_REGISTER(RF_CH) 2A
86 W_REGISTER(STATUS) 70
87 FLUSH_TX
88 W_REGISTER(RF_CH) 2A
89 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
90 W_REGISTER(RF_CH) 34
91 W_REGISTER(STATUS) 70
92 FLUSH_TX
93 W_REGISTER(RF_CH) 34
94 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
95 W_REGISTER(RF_CH) 3E
96 W_REGISTER(STATUS) 70
97 FLUSH_TX
98 W_REGISTER(RF_CH) 3E
99 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
100 W_REGISTER(RF_CH) 48
101 W_REGISTER(STATUS) 70
102 FLUSH_TX
103 W_REGISTER(RF_CH) 48
104 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
105 W_REGISTER(RF_CH) 02
106 W_REGISTER(STATUS) 70
107 FLUSH_TX
108 W_REGISTER(RF_CH) 02
109 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
110 W_REGISTER(RF_CH) 0C
111 W_REGISTER(STATUS) 70
112 FLUSH_TX
113 W_REGISTER(RF_CH) 0C
114 W_TX_PAYLOAD 20 15 05 06 73 2E 00 A1 AA
115 W_REGISTER(RF_CH) 16
116 W_REGISTER(STATUS) 70
117 FLUSH_TX
python nRF24_decode.py i6s/s1.csv | grep RF_CH | awk '{ print rshift(strtonum("0x" $3),2) }'
1
0
0
0
3
3
5
5
8
8
10
10
13
13
15
15
18
18
0
0
3
3
5
5
8
8
10
10
13
13
15
15
18
18
0
0
3
3
5
5
8
8
10
10
13
13
15
15
18
18
0
0
3
3
5
5
8
8
10
10
13
13
15
15
18
18
0
0
3
3
5
5
8
8
10
10
13
13
15
15
18
18
0
0
3
3
5
5
8
8
10
10
13
13
15
15
18
18
0
0
3
3
My ini file repository bitbucket.org/jjk836/devo10
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- jjk836
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31 Jul 2016 20:26 #52341
by jjk836
My ini file repository bitbucket.org/jjk836/devo10
Replied by jjk836 on topic Yizhan I6s does not bind
Ok, I was wrong, the hopping table is right. I'm just wondering if channel_offset could be != 0 which might break it.
My ini file repository bitbucket.org/jjk836/devo10
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