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Radiolink AT9 as a platform for Deviation?
- victzh
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Now we need to solve the problem of multiplexing both flash and radio on the same SPI and this solution is going to work. It will also work for flash-impaired F4/F7.
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- PhracturedBlue
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Possible options:
1) place all spi handling code in an interrupt that has higher priority than either the main code or protocol code
2) disable interrupts while executing spi code
3) use a queue (and probably DMA) to stage requests (along with the csn controls) to serialize requests
1 and 2 are almost the same thing when it comes down to it. The main question is what is the average length of a memory read, and will it affect protocol timing? Memory access is generally less critical than the protocol code. we could use byte-level memory reads when using the module (no high-speed transfers) and set/clear the csn for each byte. that would make the time spent in a critical section pretty low.
3 is a cool idea as it would allow a central code stream to handle all spi with minimal critical sections (just the command staging), but is a lot more complicated to setup.
Honestly, the easiest thing to do is to just disable interrupts when csn is low and re-enable them when it is high in the spi_flash code, and see what happens.
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- PhracturedBlue
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- victzh
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Regarding SPI multiplexing - I think we can arrange long SPI operations in time. You always know the time to the next protocol interrupt, so having a long operation at hand you can decide to wait over till the next time slot and you can make sure it will be integral by disabling interrupts. The chances that it will mess with protocol timing will be small if we wait first. The most frequent protocols have inactivity periods of at least 2ms, should be enough for complete SPI operation.
Staging requests in a queue probably will not work well - sometimes you need to read something from the radio and decide what to do next upon it. May be it's easier to make the time sharing a little less real time by executing protocol code not in an interrupt but in a main process by context switch. You either switch immediately if you have no SPI operation pending or after current SPI operation completes. It requires some scheduler, but should not be that complex.
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- PhracturedBlue
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i think a queue may actually work fine. the main question is: is the SPI transfer long enough that it affects the timing of the protocol. if we keep memory transfers short, I think the answer will be no.
I agree that the GUI work is beneficial. I could have hacked something that would work, but this revamp is long overdue and makes the code a lot easier to work on. It is also having the effect of freeing up quite a bit of space on the 7e/f7
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- victzh
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- FDR
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- victzh
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- PhracturedBlue
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The SST25VF032B can run at 80MHz with a 5ns setup/hold. That is plenty fast. We can ignore the setup/hold altgether with that chip. We'd probably want to have a transfer size of > 10bytes to minimize the overhead of setting the address, but otherwise, it should be fine to just disable interrupts during memory access. I don't recall which chip you were using, but I think it had similar specs.
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- FDR
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- victzh
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- PhracturedBlue
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- victzh
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- victzh
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- PhracturedBlue
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- victzh
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- PhracturedBlue
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I fixed the channels as well I think, though my testing was limited.
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- victzh
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You fixed the channels as far as I can tell. There are couple more problems beyond model layout page. First is keyboards. Second is encoder interpretation as a couple of buttons is imperfect - sometimes buttons stuck preventing all other buttons to work, sometimes in fast movement in one direction it interprets it as movement in another.
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- PhracturedBlue
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- anasm2010
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Thank you for your work Guys.
Do you think Is it possible to add a speaker to the AT9 or to replace the integrated buzzer ? (ofc if it's possible to add memory) That he can be used like the one on Taranis radio?
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