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[channel5]
safetysw=!Virt2
safetyval=-100
template=expo_dr
[mixer]
src=SW H1
dest=Ch5
curvetype=fixed
[mixer]
src=SW H1
dest=Ch5
switch=SW H1
scalar=-100
curvetype=fixed
[mixer]
src=SW H1
dest=Ch5
switch=SW H0
curvetype=fixed

[virtchan1]
template=complex
[mixer]
src=Virt1
dest=Virt1
curvetype=min/max
points=0

[virtchan2]
template=complex
[mixer]
src=!SW H1
dest=Virt2
switch=!SW H0
usetrim=0
curvetype=min/max
points=0
[mixer]
src=Virt2
dest=Virt2
switch=!SW H1
usetrim=0
curvetype=min/max
points=0
[mixer]
src=!SW H1
dest=Virt2
switch=Virt1
scalar=103
usetrim=0
muxtype=add

[trim1]
src=Virt1
pos=TRIMRH-
step=193
value=-100,

[virtchan1]
template=complex
[mixer]
src=Virt1
dest=Virt1
curvetype=min/max
points=0

[trim5]
src=Virt1
pos=TRIM_L+
step=193
value=-100,0,0,0,0,0

[virtchan2]
template=complex
[mixer]
src=GEAR0
dest=Virt2
switch=GEAR1
usetrim=0
curvetype=min/max
points=0
[mixer]
src=Virt2
dest=Virt2
switch=GEAR0
usetrim=0
curvetype=min/max
points=0
[mixer]
src=GEAR0
dest=Virt2
switch=Virt1
scalar=103
usetrim=0
muxtype=add

	static int rxaddr[ 5 ] = { /*0x2a,*/ 0x6D, 0x6A, 0x77, 0x77, 0x77 };
	nrf24_set_xn297_address( (uint8_t*)rxaddr );

static const uint8_t xn297_scramble[] = {
	0xe3, 0xb1, 0x4b, 0xea, 0x85, 0xbc, 0xe5, 0x66,
	0x0d, 0xae, 0x8c, 0x88, 0x12, 0x69, 0xee, 0x1f,
	0xc7, 0x62, 0x97, 0xd5, 0x0b, 0x79, 0xca, 0xcc
};

static void nrf24_set_xn297_address( uint8_t * addr )
{
	uint8_t rxaddr[ 6 ] = { 0x2a };
	crc_addr = 0xb5d2;
	for ( int i = 5; i > 0; --i ) {
		rxaddr[ i ] = addr[ i - 1 ] ^ xn297_scramble[ 5 - i ];
		if ( crc_en ) {
			crc_addr = CRC16_UPDATE( crc_addr, rxaddr[ i ] );
		}
	}

	// write rx address
	rx_writeregs( rxaddr, sizeof( rxaddr ) );
	// write tx address
	rxaddr[ 0 ] = 0x30;
	rx_writeregs( rxaddr, sizeof( rxaddr ) );
}

void rx_init()
{
	debugln("rx_init");
	drv_rx_init();
#define XN_TO_TX B00000010
#define XN_TO_RX B00000011
#define XN_POWER B00000001 | ( ( TX_POWER & 7 ) << 3 )
	rx_writereg( SETUP_AW, 3 );   // address size (5 bytes)
	static int rxaddr[ 5 ] = { /*0x2a,*/ 0x6D, 0x6A, 0x77, 0x77, 0x77 };
	// static int rxaddr[ 5 ] = { /*0x2a,*/ 0x55, 0x0f, 0x71, 0x77, 0x77 };
	//rx_writeregs( rxaddr, sizeof( rxaddr ) );
	// rx_writetxaddress(rxaddr);
	// rx_writerxaddress(rxaddr);
	nrf24_set_xn297_address( (uint8_t*)rxaddr );

	rx_writereg( EN_AA, 1 );      // aa enable
	rx_writereg( EN_RXADDR, 1 );  // pipe 0 only
	rx_writereg( RF_SETUP, XN_POWER );    // power / data rate / lna
	rx_writereg( RX_PW_P0, PAYLOAD_SIZE );  // payload size
	rx_writereg( SETUP_RETR, 0 ); // no retransmissions (redundant?)
	rx_writereg( SETUP_AW, 3 );   // address size (5 bytes)
	rx_command( FLUSH_RX );
	rx_writereg( RF_CH, BIND_CH );      // bind on channel 0
	debugln("Read RF_CH: 0x%x", rx_readreg(RF_CH));

	rx_writereg( 0x1d, B00111000 );   // 64 bit payload, software ce
	// static uint8_t cehigh_regs[ 2 ] = { 0xFD, 0 }; // internal CE high command, 0 also required
	// rx_writeregs( cehigh_regs, sizeof( cehigh_regs ) );

	rx_writereg( 0, XN_TO_RX );   // power up, crc enabled, rx mode

	int rxcheck = rx_readreg( 0x0f ); // rx address pipe 5
	// should be 0xc6
	extern void failloop( int );
	if ( rxcheck != 0xc6 ) {
		failloop( 3 );
	}
}